65816 CheatSheet

Register

NameShortLength
AccumulatorA (B, C)8/16
Index register (X)X8/16
Index register (Y)Y8/16
Stack pointerSP16
Program counterPC16
Processor statusP8
Direct pointerD16
Program bank registerPB (K)8
Data bank registerDB (B)8

Status flag

bitNameDescription
7NNegative flag
6VOverflow flag
5MMemory select (0=16 / 1=8)
5R(Emulation mode) Reserved (always 1)
4XIndex register select (0=16 / 1=8)
4B(Emulation mode) Break flag (0=IRQ / 1=BRK)
3DDecimal mode (0=Binary / 1=Decimal)
2IIRQ disable (0=IRQ Enable / 1=IRQ Disable)
1ZZero flag
0CCarry flag
-EEmulation flag (0=Native / 1=Emulation)

Addressing mode

Name Short Description Syntax
Implied
Accumulator A
Stack S
Immediate #imm operand #$01
Direct page (Zero page) dp [D + dp] $01
Direct page Indexed, X dp,X [D + dp + X] $01,X
Direct page Indexed, Y dp,Y [D + dp + Y] $01,Y
Direct page Indirect (dp) [DB + [D + dp]] ($01)
Direct page Indexed Indirect, X (dp,X) [DB + [D + dp + X]] ($01,X)
Direct page Indirect Indexed, Y (dp),Y [DB + [D + dp] + Y] ($01),Y
Direct page Indirect Long [dp] [[D + dp]] [$01]
Direct page Indirect Long Indexed, Y [dp],Y [[D + dp] + Y] [$01],Y
Absolute abs [DB + abs] $0123
Absolute Indexed, X abs,X [DB + abs + X] $0123,X
Absolute Indexed, Y abs,Y [DB + abs + Y] $0123,Y
Absolute Indirect (abs) [[PB + abs]] ($0123)
Absolute Indexed Indirect (abs,X) [[PB + abs + X]] ($0123,X)
Absolute Indirect Long [abs] [[abs]] [$0123]
Absolute Long long [long] $012345
Absolute Long Indexed, X long,X [long + X] $012345,X
Relative rel [PB + PC + rel] #$01
Relative Long rlong [PB + PC + rlong] #$0123
Stack Relative sr,S [SP + sr] $01,S
Stack Relative Indirect Indexed, Y (sr,S),Y [DB + [SP + sr] + Y] ($01,S),Y
Block Move xyc [dst:Y] = [src:X] dst, src

Instruction Set (Binary)

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
00 BRK S27*8 ORA (dp,X)26*2,4 COP S27*8 ORA sr,S24*2 TSB dp25*3,4 ORA dp23*2,4 ASL dp25*3,4 ORA [dp]26*2,4 PHP S13 ORA #imm22*1,2 ASL A12 PHD S14 TSB abs36*3 ORA abs34*2 ASL abs36*3 ORA long45*2
10 BPL rel22*6,7 ORA (dp),Y25*2,4,5 ORA (dp)25*2,4 ORA (sr,S),Y27*2 TRB dp25*3,4 ORA dp,X24*2,4 ASL dp,X26*3,4 ORA [dp],Y26*2,4 CLC12 ORA abs,Y34*2,5 INC A12 TCS12 TRB abs36*3 ORA abs,X34*2,5 ASL abs,X37*3 ORA long,X45*2
20 JSR abs36 AND (dp,X)26*2,4 JSL long48 AND sr,S24*2 BIT dp23*2,4 AND dp23*2,4 ROL dp25*3,4 AND [dp]26*2,4 PLP S14 AND #imm22*1,2 ROL A12*2 PLD S15 BIT abs34*2 AND abs34*2 ROL abs36*3 AND long45*2
30 BMI rel22*6,7 AND (dp),Y25*2,4,5 AND (dp)25*2,4 AND (sr,S),Y27*2 BIT dp,X24*2,4 AND dp,X24*2,4 ROL dp,X26*3,4 AND [dp],Y26*2,4 SEC12 AND abs,Y34*2,5 DEC A12 TSC12 BIT abs,X34*2 AND abs,X34*2 ROL abs,X37*3 AND long,X45*2
40 RTI S16*8 EOR (dp,X)26*2,4 WDM #imm22 EOR sr,S24*2 MVP xyc37 EOR dp23*2,4 LSR dp25*3,4 EOR [dp]26*2,4 PHA S13*2 EOR #imm22*1,2 LSR A12 PHK S13 JMP abs33 EOR abs34*2 LSR abs36*3 EOR long45*2
50 BVC rel22*6,7 EOR (dp),Y25*2,4,5 EOR (dp)25*2,4 EOR (sr,S),Y27*2 MVN xyc37 EOR dp,X24*2,4 LSR dp,X26*3,4 EOR [dp],Y26*2,4 CLI12 EOR abs,Y34*2,5 PHY S13*2 TCD12 JML long44 EOR abs,X34*2 LSR abs,X37*3 EOR long,X45*2
60 RTS S16 ADC (dp,X)26*2,4 PER rlong36 ADC sr,S24*2 STZ dp23*2,4 ADC dp23*2,4 ROR dp25*3,4 ADC [dp]26*2,4 PLA S14*2 ADC #imm22*1,2 ROR A12 RTL S16 JMP (abs)35 ADC abs34*2 ROR abs36*3 ADC long45*2
70 BVS rel22*6,7 ADC (dp),Y25*2,4,5 ADC (dp)25*2,4 ADC (sr,S),Y27*2 STZ dp,X24*2,4 ADC dp,X24*2,4 ROR dp,X26*3,4 ADC [dp],Y26*2,4 SEI12 ADC abs,Y34*2,5 PLY S14*2 TDC12 JMP (abs,X)36 ADC abs,X34*2 ROR abs,X37*3 ADC long,X45*2
80 BRA rel23*6,7 STA (dp,X)26*2,4 BRL rlong34 STA sr,S24*2 STY dp23*2,4 STA dp23*2,4 STX dp23*2,4 STA [dp]26*2,4 DEY12 BIT #imm22*1,2 TXA12 PHB S13 STY abs34*2 STA abs34*2 STX abs34*2 STA long45*2
90 BCC rel22*6,7 STA (dp),Y26*2,4,5 STA (dp)25*2,4 STA (sr,S),Y27*2 STY dp,X24*2,4 STA dp,X24*2,4 STX dp,Y24*2,4 STA [dp],Y26*2,4 TYA12 STA abs,Y35*2,5 TXS12 TXY12 STZ abs34*2 STA abs,X35*2 STZ abs,X35*2 STA long,X45*2
A0 LDY #imm22*1,2 LDA (dp,X)26*2,4 LDX #imm22*1,2 LDA sr,S24*2 LDY dp23*2,4 LDA dp23*2,4 LDX dp23*2,4 LDA [dp]26*2,4 TAY12 LDA #imm22*1,2 TAX12 PLB S14 LDY abs34*2 LDA abs34*2 LDX abs34*2 LDA long45*2
B0 BCS rel22*6,7 LDA (dp),Y25*2,4,5 LDA (dp)25*2,4 LDA (sr,S),Y27*2 LDY dp,X24*2,4 LDA dp,X24*2,4 LDX dp,Y24*2,4 LDA [dp],Y26*2,4 CLV12 LDA abs,Y34*2,5 TSX12 TYX12 LDY abs,X34*2 LDA abs,X34*2 LDX abs,Y34*2,5 LDA long,X45*2
C0 CPY #imm22*1,2 CMP (dp,X)26*2,4 REP #imm23 CMP sr,S24*2 CPY dp23*2,4 CMP dp23*2,4 DEC dp25*3,4 CMP [dp]26*2,4 INY12 CMP #imm22*1,2 DEX12 WAI13 CPY abs34*2 CMP abs34*2 DEC abs36*3 CMP long45*2
D0 BNE rel22*6,7 CMP (dp),Y25*2,4,5 CMP (dp)25*2,4 CMP (sr,S),Y27*2 PEI (dp)26*4 CMP dp,X24*2,4 DEC dp,X26*3,4 CMP [dp],Y26*2,4 CLD12 CMP abs,Y34*2,5 PHX S13*2 STP13 JML [abs]36 CMP abs,X34*2 DEC abs,X37*3 CMP long,X45*2
E0 CPX #imm22*1,2 SBC (dp,X)26*2,4 SEP #imm23 SBC sr,S24*2 CPX dp23*2,4 SBC dp23*2,4 INC dp25*3,4 SBC [dp]26*2,4 INX12 SBC #imm22*1,2 NOP12 XBA13 CPX abs34*2 SBC abs34*2 INC abs36*3 SBC long45*2
F0 BEQ rel22*6,7 SBC (dp),Y25*2,4,5 SBC (dp)25*2,4 SBC (sr,S),Y27*2 PEA abs35 SBC dp,X24*2,4 INC dp,X26*3,4 SBC [dp],Y26*2,4 SED12 SBC abs,Y34*2,5 PLX S14*2 XCE12 JSR (abs,X)38 SBC abs,X34*2 INC abs,X37*3 SBC long,X45*2

Legend
Byte / Cycle

  1. Add 1 byte if register is 16bit length mode.
  2. Add 1 cycle if register is 16bit length mode.
  3. Add 2 cycle if register is 16bit length mode.
  4. Add 1 cycle if lower byte of D register is not zero.
  5. Add 1 cycle if index register is 16bit, or write access, or crosses page boundary.
  6. Add 1 cycle if branch is taken.
  7. Add 1 cycle if branch is taken and page boundary is crossed in emulation mode.
  8. Add 1 cycle if native mode.

Instruction Set (Addressing)

Mnemonic imp A S #imm dp dp,X dp,Y (dp) (dp,X) (dp),Y [dp] [dp],Y abs abs,X abs,Y (abs) (abs,X) [abs] long long,X rel rlong sr,S (sr,S),Y xyc Flags
ADC 6965757261716777 6D7D796F7F6373 NV----ZC
AND 2925353221312737 2D3D392F3F2333 N-----Z-
ASL 0A0616 0E1E N-----ZC
BCC 90 --------
BCS B0 --------
BEQ F0 --------
BGE B0 --------
BIT 892434 2C3C NV----Z- (N=opr.bit7, V=opr.bit6) / #imm : ------Z-
BLT 90 --------
BMI 30 --------
BNE D0 --------
BPL 10 --------
BRA 80 --------
BRK 00 ----DI-- (D=0, I=1)
BRL 82 --------
BVC 50 --------
BVS 70 --------
CLC 18 -------C (C=0)
CLD D8 ----D--- (D=0)
CLI 58 -----I-- (I=0)
CLV B8 -V------ (V=0)
CMA C9C5D5D2C1D1C7D7 CDDDD9CFDFC3D3 N-----ZC
CMP C9C5D5D2C1D1C7D7 CDDDD9CFDFC3D3 N-----ZC
COP 02 ----DI-- (D=0, I=1)
CPX E0E4 EC N-----ZC
CPY C0C4 CC N-----ZC
DEA 3A N-----Z-
DEC 3AC6D6 CEDE N-----Z-
DEX CA N-----Z-
DEY 88 N-----Z-
EOR 4945555241514757 4D5D594F5F4353 N-----Z-
INA 1A N-----Z-
INC 1AE6F6 EEFE N-----Z-
INX E8 N-----Z-
INY C8 N-----Z-
JML DC5C --------
JMP 4C6C7CDC5C --------
JSL 22 --------
JSR 20FC22 --------
LDA A9A5B5B2A1B1A7B7 ADBDB9AFBFA3B3 N-----Z-
LDX A2A6B6 AEBE N-----Z-
LDY A0A4B4 ACBC N-----Z-
LSR 4A4656 4E5E N-----ZC (N=0)
MVN 54 --------
MVP 44 --------
NOP EA --------
ORA 0905151201110717 0D1D190F1F0313 N-----Z-
PEA F4 --------
PEI D4 --------
PER 62 --------
PHA 48 --------
PHB 8B --------
PHD 0B --------
PHK 4B --------
PHP 08 --------
PHX DA --------
PHY 5A --------
PLA 68 N-----Z-
PLB AB N-----Z-
PLD 2B N-----Z-
PLP 28 NVMXDIZC
PLX FA N-----Z-
PLY 7A N-----Z-
REP C2 NVMXDIZC
ROL 2A2636 2E3E N-----Z-
ROR 6A6676 6E7E N-----Z-
RTI 40 NVMXDIZC
RTL 6B --------
RTS 60 --------
SBC E9E5F5F2E1F1E7F7 EDFDF9EFFFE3F3 NV----ZC
SEC 38 -------C (C=1)
SED F8 ----D--- (D=1)
SEI 78 -----I-- (I=1)
SEP E2 NVMXDIZC
STA 85959281918797 8D9D998F9F8393 --------
STP DB --------
STX 8696 8E --------
STY 8494 8C --------
STZ 6474 9C9E --------
SWA EB N-----Z-
TAD 5B N-----Z-
TAS 1B --------
TAX AA N-----Z-
TAY A8 N-----Z-
TCD 5B N-----Z-
TCS 1B --------
TDA 7B N-----Z-
TDC 7B N-----Z-
TRB 14 1C ------Z-
TSA 3B N-----Z-
TSB 04 0C ------Z-
TSC 3B N-----Z-
TSX BA N-----Z-
TXA 8A N-----Z-
TXS 9A --------
TXY 9B N-----Z-
TYA 98 N-----Z-
TYX BB N-----Z-
WAI CB --------
WDM 42 --------
XBA EB N-----Z-
XCE FB -------C (C=E, E=C)

Vector Locations

AddressModeLabel
$00FFE0Native(Reserved)
$00FFE2Native(Reserved)
$00FFE4NativeCOP
$00FFE6NativeBRK
$00FFE8NativeABORT
$00FFEANativeNMI
$00FFECNative(Reserved)
$00FFEENativeIRQ
$00FFF0Emulation(Reserved)
$00FFF2Emulation(Reserved)
$00FFF4EmulationCOP
$00FFF6Emulation(Reserved)
$00FFF8EmulationABORT
$00FFFAEmulationNMI
$00FFFCEmulationRESET
$00FFFEEmulationIRQ / BRK